View UPD16448A_1253732.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document no. s11712ej3v0ds00 (3rd edition) date published august 1998 ns cp(k) printed in japan source driver for 240-output tft-lcd (navigation, automobile lcd-tv) data sheet mos integrated circuit m m m m pd16448a 1998 the mark h h h h shows major revised points. m pd16448a is a source driver for tft liquid crystal panels. this ic consists of a multiplexer circuit supporting a variety of pixel arrays, a shift register that generates sampling timing, and two sample and hold circuits that sample analog voltages. because the two sample and hold circuits alternately execute sampling and holding, a high definition can be obtained. in addition, simultaneous sampling and successive sampling are automatically selected according to the pixel array of the lcd panel. it is ideal for a wide range of applications, including navigation systems and automobile lcd- tvs. features can be driven on 5 v (dynamic range: 4.3 v, v dd2 = 5.0 v) 240-output f max. = 18 mhz (v dd1 = 3.0 v) simultaneous/successive sampling selectable according to pixel array simultaneous sampling: vertical stripe successive sampling: delta array, mosaic array two sample and hold circuits low output deviation between pins ( 20 mv max.) stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit left and right shift selected by r/l pin single-side mounting possible ordering information part number package m pd16448an- tcp (tab package) remark the dimensions of tcp are custom-made. please consult nec for details. the information in this document is subject to change without notice.
2 m m m m pd16448a block diagram cli 1 to 3 r/l 240-bit shift register sthr sthl multi- plexer inh reset c 2 c 1 c 3 mp/th mp/1.5 240-bit level shifter h 1 h 240 ..................................................................................................... 240-bit sample and hold buffer +3.3 v v dd1 v ss1 v ss2 v ss3 gnd +5.0 v v dd2 3 sample and hold circuit and output circuit swa1 c h1 + C swb1 swa2 c h2 + C swb2 h n video line
3 m m m m pd16448a pin configration ( m m m m pd16448a n-xxx) remark this figure does not spesify the tcp package. c 1 c 2 c 3 v dd2 v dd1 sthl mp/th mp/1.5 r/l reset inh cli 1 cli 2 cli 3 test sthr v ss1 v ss3 v ss2 h 240 h 239 h 238 h 237 h 5 h 4 h 3 h 2 h 1 copper foll suface h
4 m m m m pd16448a 1. pin description symbol name function c 1 to c 3 video signal input input r, g, and b video signals. h 1 to h 240 video signal output video signal output pins. output sampled and held video signals during horizontal period. sthr sthl cascade i/o start pulse i/o pins of sample hold timing. sthr serves as an input pin and sthl, as an output pin, in the case of right shift. in the case of left shift, sthl serves as an input pin, and sthr, as an output pin. cli 1 cli 2 cli 3 shift clock input a start pulse is read at the rising edge of cli 1 . sampling pulse shp n is generated at the rising edge of cli 1 through cli 3 during successive sampling, and at the rising edge of cli 1 during simultaneous sampling (for details, refer to the timing charts in 2.function description ). inh inhibit input selects a multiplexer and one of the two sample and hold circuits at the falling edge. reset reset input resets the select counter of the multiplexer and the selector circuit of the two sample and hold circuits when it goes high. after reset, the multiplexer is turned off, so sure to input one pulse of the inh signal before inputting the video signal. if the video signal is input without the inh signal, sampling is not executed. four types of color filter arrays can be supported by combination of mp/th and mp/1.5. mode mp/th mp/1.5 mp/th multiplexer circuit select input (1) vertical stripe array l l single-side delta array l h mosaic array h l double-side delta array h h mp/1.5 multiplexer circuit select input (2) r/l shift direction select input r/l = h; right shift: sthr ? h 1 ? h 240 ? sthl r/l = l; left shift: sthl ? h 240 ? h 1 ? sthr v dd1 logic power supply 3.0 v to 5.5 v v dd2 driver power supply 5.0 v 0.5 v v ss1 logic ground connect this pin to ground of system. v ss2 driver ground connect this pin to ground of system. v ss3 driver ground connect this pin to ground of system. test test pin fix this pin to l.
5 m m m m pd16448a 2. function description 2.1 multiplexer circuit this circuit selects rgb video signals input to the c 1 , c 2 , and c 3 pins according to the pixel array of the liquid crystal panel, and outputs the signals to the h 1 through h 240 pins. vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the mp/th and mp/1.5 pins. 2.1.1 vertical stripe array mode (mp/th = l, mp/1.5 = l) in this mode, the relation between video signals c 1 , c 2 , and c 3 , and output pins is as shown below. this mode is used to drive a panel of vertical stripe array. in this mode, the multiplexer circuit is in the through status. relation between video signals c 1 , c 2 , and c 3 , and output pins (during right shift) line no. (number of inhs) reset inh h 1 (h 240 )h 2 (h 239 )h 3 (h 238 )h 4 (h 237 )h 239 (h 2 )h 240 (h 1 ) 0hl sampling c 1 (c 3 ) sampling c 2 (c 2 ) sampling c 3 (c 1 ) sampling c 1 (c 3 ) sampling c 2 (c 2 ) sampling c 3 (c 1 ) 1l output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) 2l output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) 3l output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) : : : : : : : : : : : : : : : : : : ( ) indicates the case of left shift. pixel arrangement of vertical stripe array and multiplexer operation r ? c 1 b ? c 2 g ? c 3 pd16448a right shift (r/l = "h"), mp/th = "l", mp/1.5 = "l" m h 1 r r r r r b b b b b g g g g g r r r r r b b b b b g g g g g r r r r r h 2 h 3 h 4 h 5 h 6 h 7
6 m m m m pd16448a timing chart of vertical stripe array reset inh h 1 (h 240 ) sampling input data ? output un- defined c 1 (c 3 )c 1 (c 3 )c 1 (c 3 )c 1 (c 3 ) c 1 (c 3 ) undefined c 1 (c 3 ) c 1 (c 3 ) c 1 (c 3 ) c 1 (c 3 ) c 1 (c 3 ) h 2 (h 239 ) sampling input data ? output un- defined c 2 (c 2 )c 2 (c 2 )c 2 (c 2 )c 2 (c 2 ) c 2 (c 2 ) undefined c 2 (c 2 ) c 2 (c 2 ) c 2 (c 2 ) c 2 (c 2 ) c 2 (c 2 ) h 3 (h 238 ) sampling input data ? output un- defined c 3 (c 1 )c 3 (c 1 )c 3 (c 1 )c 3 (c 1 ) c 3 (c 1 ) undefined c 3 (c 1 ) c 3 (c 1 ) c 3 (c 1 ) c 3 (c 1 ) c 3 (c 1 ) h 239 (h 2 ) sampling input data ? output un- defined c 2 (c 2 )c 2 (c 2 )c 2 (c 2 )c 2 (c 2 ) c 2 (c 2 ) undefined c 2 (c 2 ) c 2 (c 2 ) c 2 (c 2 ) c 2 (c 2 ) c 2 (c 2 ) h 240 (h 1 ) sampling input data ? output un- defined c 3 (c 1 )c 3 (c 1 )c 3 (c 1 )c 3 (c 1 ) c 3 (c 1 ) undefined c 3 (c 1 ) c 3 (c 1 ) c 3 (c 1 ) c 3 (c 1 ) c 3 (c 1 )
7 m m m m pd16448a 2.1.2 single-side delta array mode (mp/th = l, mp/1.5 = h) relation between video signals c 1 , c 2 , and c 3 , and output pins line no. (number of inhs) reset inh h 1 (h 240 )h 2 (h 239 )h 3 (h 238 )h 4 (h 237 )h 239 (h 2 )h 240 (h 1 ) 0 h l undefined undefined undefined undefined undefined undefined 1l sampling c 1 (c 3 ) sampling c 2 (c 2 ) sampling c 3 (c 1 ) sampling c 1 (c 3 ) sampling c 2 (c 2 ) sampling c 3 (c 1 ) 2l output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) 3l output c 2 (c 1 ) output c 3 (c 3 ) output c 1 (c 2 ) output c 2 (c 1 ) output c 3 (c 3 ) output c 1 (c 2 ) 4l output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) 5l output c 2 (c 1 ) output c 3 (c 3 ) output c 1 (c 2 ) output c 2 (c 1 ) output c 3 (c 3 ) output c 1 (c 2 ) ( ) indicates the case of left shift. pixel arrangement of single-side delta array and multiplexer operation r ? c 1 b ? c 2 g ? c 3 pd16448a right shift (r/l = h), mp/th = "l", mp/1.5 = "h" m h 1 rbgrbgr h 2 h 3 h 4 h 5 h 6 h 7 bgrbgrb g rbgrbgr bgrbgrb g rbgrbgr bgrbgrb g rbgrbgr
8 m m m m pd16448a timing chart of single-side delta array reset inh h 1 (h 240 ) sampling input data ? output un- defined undefined c 1 (c 3 )c 2 (c 1 )c 1 (c 3 ) c 2 (c 1 ) undefined c 1 (c 3 ) c 2 (c 1 ) c 1 (c 3 ) c 2 (c 1 ) h 2 (h 239 ) sampling input data ? output un- defined undefined c 2 (c 2 )c 3 (c 3 )c 2 (c 2 ) c 3 (c 3 ) undefined undefined c 2 (c 2 ) c 3 (c 3 ) c 2 (c 2 ) c 3 (c 3 ) h 3 (h 238 ) sampling input data ? output un- defined undefined c 3 (c 1 )c 1 (c 2 )c 3 (c 1 ) c 1 (c 2 ) undefined undefined c 3 (c 1 ) c 1 (c 2 ) c 3 (c 1 ) c 1 (c 2 ) h 239 (h 2 ) sampling input data ? output un- defined undefined c 2 (c 2 )c 3 (c 3 )c 2 (c 2 ) c 3 (c 3 ) undefined undefined c 2 (c 2 ) c 3 (c 3 ) c 2 (c 2 ) c 3 (c 3 ) h 240 (h 1 ) sampling input data ? output un- defined undefined c 3 (c 1 )c 1 (c 2 )c 3 (c 1 ) c 1 (c 2 ) undefined undefined c 3 (c 1 ) c 1 (c 2 ) c 3 (c 1 ) c 1 (c 2 )
9 m m m m pd16448a 2.1.3 double-side delta array mode (mp/th = h, mp/1.5 = h) because the pad pitch of the m pd16448a is designed so that the ic is mounted on one side, the output pitch must be expanded on the tcp if the ic is mounted on both sides. relation between video signals c 1 , c 2 , and c 3 , and output pins line no. (number of inhs) reset inh h 1 (h 240 )h 2 (h 239 )h 3 (h 238 )h 4 (h 237 )h 239 (h 2 )h 240 (h 1 ) 0 h l undefined undefined undefined undefined undefined undefined 1l sampling c 2 (c 3 ) sampling c 3 (c 2 ) sampling c 1 (c 1 ) sampling c 2 (c 3 ) sampling c 3 (c 2 ) sampling c 1 (c 1 ) 2l output c 2 (c 3 ) output c 3 (c 2 ) output c 1 (c 1 ) output c 2 (c 3 ) output c 3 (c 2 ) output c 1 (c 1 ) 3l output c 1 (c 1 ) output c 2 (c 3 ) output c 3 (c 2 ) output c 1 (c 1 ) output c 2 (c 3 ) output c 3 (c 2 ) 4l output c 2 (c 3 ) output c 3 (c 2 ) output c 1 (c 1 ) output c 2 (c 3 ) output c 3 (c 2 ) output c 1 (c 1 ) 5l output c 1 (c 1 ) output c 2 (c 3 ) output c 3 (c 2 ) output c 1 (c 1 ) output c 2 (c 3 ) output c 3 (c 2 ) ( ) indicates the case of left shift. pixel arrangement of double-side delta array and multiplexer operation r ? c 1 b ? c 2 g ? c 3 pd16448a right shift (r/l = "h"), mp/th = "h", mp/1.5 = "h" m h 1 rbgrbgr h 2 h 3 h 3 bgrbgrb g rbgrbgr rbgrbgr bgrbgrb g g ? c 1 r ? c 2 b ? c 3 pd16448a left shift (r/l = "l"), mp/th = "h", mp/1.5 = "h" m h 240 h 239 h 238 h 237
10 m m m m pd16448a timing chart of double-side delta array reset inh h 1 (h 240 ) sampling input data ? output un- defined undefined c 2 (c 3 )c 1 (c 1 )c 2 (c 3 ) c 1 (c 1 ) undefined c 2 (c 3 ) c 1 (c 1 ) c 2 (c 3 ) c 1 (c 1 ) h 2 (h 239 ) sampling input data ? output un- defined undefined c 3 (c 2 )c 2 (c 3 )c 3 (c 2 ) c 2 (c 3 ) undefined undefined c 3 (c 2 ) c 2 (c 3 ) c 3 (c 2 ) c 2 (c 3 ) h 3 (h 238 ) sampling input data ? output un- defined undefined c 1 (c 1 )c 3 (c 2 )c 1 (c 1 ) c 3 (c 2 ) undefined undefined c 1 (c 1 ) c 3 (c 2 ) c 1 (c 1 ) c 3 (c 2 ) h 239 (h 2 ) sampling input data ? output un- defined undefined c 3 (c 2 )c 2 (c 3 )c 3 (c 2 ) c 2 (c 3 ) undefined undefined c 3 (c 2 ) c 2 (c 3 ) c 3 (c 2 ) c 2 (c 3 ) h 240 (h 1 ) sampling input data ? output un- defined undefined c 1 (c 1 )c 3 (c 2 )c 1 (c 1 ) c 3 (c 2 ) undefined undefined c 1 (c 1 ) c 3 (c 2 ) c 1 (c 1 ) c 3 (c 2 )
11 m m m m pd16448a 2.1.4 mosaic array mode (mp/th = h, mp/1.5 = l) relation between video signals c 1 , c 2 , and c 3 , and output pins line no. (number of inhs) reset inh h 1 (h 240 )h 2 (h 239 )h 3 (h 238 )h 4 (h 237 )h 239 (h 2 )h 240 (h 1 ) 0 h l undefined undefined undefined undefined undefined undefined 1l sampling c 1 (c 3 ) sampling c 2 (c 2 ) sampling c 3 (c 1 ) sampling c 1 (c 3 ) sampling c 2 (c 2 ) sampling c 3 (c 1 ) 2l output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) 3l output c 3 (c 2 ) output c 1 (c 1 ) output c 2 (c 3 ) output c 3 (c 2 ) output c 1 (c 1 ) output c 2 (c 3 ) 4l output c 2 (c 1 ) output c 3 (c 3 ) output c 1 (c 2 ) output c 2 (c 1 ) output c 3 (c 3 ) output c 1 (c 2 ) 5l output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) output c 1 (c 3 ) output c 2 (c 2 ) output c 3 (c 1 ) : : : : : : : : : : : : : : : : : : ( ) indicates the case of left shift. pixel arrangement of mosaic array and multiplexer operation r ? c 1 g ? c 2 b ? c 3 pd16448a right shift (r/l = "h"), mp/th = "h", mp/1.5 = "l" m h 1 r b g r b g r b g r b g r b g r b g r b g r b g r b g r b g r b g r b h 2 h 3 h 4 h 5 h 6 h 7
12 m m m m pd16448a timing chart of mosaic array reset inh h 1 (h 240 ) sampling input data ? output un- defined undefined c 1 (c 3 )c 3 (c 2 )c 2 (c 1 ) c 1 (c 3 ) undefined c 1 (c 3 ) c 3 (c 2 ) c 2 (c 1 ) c 1 (c 3 ) h 2 (h 239 ) sampling input data ? output un- defined undefined c 2 (c 2 )c 1 (c 1 )c 3 (c 3 ) c 2 (c 2 ) undefined undefined c 2 (c 2 ) c 1 (c 1 ) c 3 (c 3 ) c 2 (c 2 ) h 3 (h 238 ) sampling input data ? output un- defined undefined c 3 (c 1 )c 2 (c 3 )c 1 (c 2 ) c 3 (c 1 ) undefined undefined c 3 (c 1 ) c 2 (c 3 ) c 1 (c 2 ) c 3 (c 1 ) h 239 (h 2 ) sampling input data ? output un- defined undefined c 2 (c 2 )c 1 (c 1 )c 3 (c 3 ) c 2 (c 2 ) undefined undefined c 2 (c 2 ) c 1 (c 1 ) c 3 (c 3 ) c 2 (c 2 ) h 240 (h 1 ) sampling input data ? output un- defined undefined c 3 (c 1 )c 2 (c 3 )c 1 (c 2 ) c 3 (c 1 ) undefined undefined c 3 (c 1 ) c 2 (c 3 ) c 1 (c 2 ) c 3 (c 1 )
13 m m m m pd16448a 2.1.5 relation between shift clock cli n and internal sampling pulse shp n (1) simultaneous sampling (( ) indicates the case of left shift.) cli 1 sthr (sthl) shp 1 (shp 240 ) c 1 sampling shp 2 (shp 239 ) c 2 sampling shp 3 (shp 238 ) c 3 sampling shp 4 (shp 237 ) c 1 sampling shp 5 (shp 236 ) c 2 sampling shp 6 (shp 235 ) c 3 sampling remark c 1 through c 3 are sampled while shp n is h. (2) successive sampling (( ) indicates the case of left shift.) cli 3 sthr (sthl) shp 1 (shp 240 ) c 1 sampling shp 2 (shp 239 ) c 2 sampling shp 3 (shp 238 ) c 3 sampling shp 4 (shp 237 ) c 1 sampling shp 5 (shp 236 ) c 2 sampling shp 6 (shp 235 ) c 3 sampling cli 1 cli 2 3-phase clock remarks 1. input a three-phase clock to shift clock pins cli 1 through cli 3 . 2. the video signals (c 1 , c 2 , and c 3 ) are sampled while shp n is h.
14 m m m m pd16448a 2.2 sample and hold circuit the sample and hold circuit samples and holds the video input signals c 1 through c 3 selected by the multiplexer circuit in the timing shown below. swa1 through swb2 are reset by the reset signal and change at the rising and falling edges of the inh signal. (refer to block diagram .) reset data swa1 swa2 swb1 swb2 inh un- defined undefined on on
15 m m m m pd16448a 2.3 write operation timing the sampled video signals are written to the lcd panel by output currents i vol and i voh via output buffer. the dynamic range is 4.3 v min . (v dd2 = 5.0 v). while inh = h, do not stop shift clocks cli 1 through cli 3 . the output operation of this ic is controlled by inh signals. inh = hiz inh = connected with internal circuit (switch sample and hold circuit at the falling edge.) therefore, performing vcom inversion while inh = l causes current flow to these ic output pins, which may result in malfunction. perform vcom in version during inh = h (hi-z) and start output operation of the next line after the vcom signal is stable enough to operate. make sure to evaluate this output operation sufficiently. inh vcom output voltage 1 horizontal period 1 horizontal period h
16 m m m m pd16448a [cautions on use] 1. turn on power to v dd1 , logic input, v dd2 , and video signal input in that order to prevent destruction due to latchup, and turn off power in the reverse sequence. observe this power sequence even during the transition period. 2. this ic is designed to input successive signals such as chrome signals. the input band of the video signals is designed to be 9 mhz max . if video signals faster than that are input, display is not performed correctly. 3. insert a bypass capacitor of 0.1 m m m m f between v dd1 and v ss1 and between v dd2 and v ss2 . if the power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage fluctuates. 4. display may not be correctly performed if noise is superimposed on the start pulse pin. therefore, be sure to input a reset signal during the vertical blanking period. 5. even if the start pulse width is extended by half a clock or more, sampling start timing shp 1 is not affected, and the sampling operation is performed normally. 6. when the multiplexer circuit is used in the vertical stripe mode, c 1 , c 2 , and c 3 are simultaneously sampled at the rising edge of shp n . internally, however, only cli 1 is valid. therefore, input a shift clock to cli 1 only. at this time, keep the cli 2 and cli 3 pins to "l". when using the multiplexer circuit in the delta array mode or mosaic array mode, c 1 , c 2 , and c 3 are sequentially sampled. input a three-phase clock to cli 1 through cli 3 . (for the sampling timing, refer to 2. function description.) 7. the recommended timing of t r-1 and pw res on starting is shown below. (the following timing chart shows simultaneous sampling.) an inh pulse width of at least 5 clocks is required to reset the internal logic. unless the inh pulse is input after reset, sampling is not performed in the correct sequence. cli 1 reset inh sthr (sthl) shp 1 to 3 shp 4 to 6 shp 7 to 9 12345 123 pw res t isetup t ihold t rCi pw inh : 5 clocks min. 3 clocks min.
17 m m m m pd16448a 3.electrical characteristics absolute maximum ratings (t a = 25 c, v ss1 = v ss2 = 0 v) parameter symbol condition ratings unit logic supply voltage v dd1 -0.5 to +7.0 v driver supply voltage v dd2 -0.5 to +7.0 v logic input voltage v i -0.5 to v dd1 +0.5 v video input voltage v vi c 1 , c 2 , c 3 -0.5 to v dd2 +0.5 v logic output voltage v 01 -0.5 to v dd1 +0.5 v driver output voltage v 02 -0.5 to v dd2 +0.5 v driver output current i o2 10 ma operating temperature range t a -30 to +85 c storage temperature range t stg -65 to +125 c caution if the absolute maximum rating of even one of the above parameters is exceeded eve momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating conditions (t a = -30 to +85 c, v ss1 = v ss2 = 0 v) parameter symbol min. typ. max. unit logic supply voltage v dd1 3.0 3.3 5.5 v driver supply voltage v dd2 4.5 5.0 5.5 v video input voltage v vi v ss2 + 0.35 v dd2 - 0.35 v driver output voltage v 02 v ss2 + 0.35 v dd2 - 0.35 v input voltage, high v ih 0.7 v dd1 v dd1 v input voltage, low v il 00.3 v dd1 v
18 m m m m pd16448a electrical characteristics (t a = -30 to +85 c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit maximum video signal output voltage v voh v dd 2 - 0.35 v minimum video signal output voltage v vol 0.35 v logic output voltage, high v loh sthl, sthr pins i oh = -1.0 ma 0.9 v dd1 v logic output voltage, low v lol sthl, sthr pins i ol = 1.0 ma 0.1 v dd1 v video signal output current, high i voh inh = l v o = v dd2 - 0.5 v -0.20 -0.08 ma video signal output current, low i vol inh = l v of = 1.0 v, v o = 0.5 v -0.08 0.20 ma reference voltage 1 v ref1 v dd2 = 5.0 v, t a = 25 c v vi = 0.5 v 0.49 v reference voltage 2 v ref2 v dd2 = 5.0 v, t a = 25 c v vi = 2.0 v 1.99 v reference voltage 3 v ref3 v dd2 = 5.0 v, t a = 25 c v vi = 3.5 v 3.49 v output voltage deviation 1 d v vo1 v dd2 = 5.0 v, t a = 25 c v vi = 0.5 v 20 mv output voltage deviation 2 d v vo2 v dd2 = 5.0 v, t a = 25 c v vi = 2.0 v 20 mv output voltage deviation 3 d v vo3 v dd2 = 5.0 v, t a = 25 c v vi = 3.5 v 20 mv logic input leakage current i ll 1.0 m a video input leakage current i vl 10 m a v dd1 = 3.3 0.3 v 2.5 logic dynamic current consumption i dd1 f cli = 14 mhz v vi = 2.0 v, no load f inh = 15.4 khz pw inh = 5.0 m s v dd1 = 5.0 0.5 v 4.0 ma driver dynamic current consumption i dd2 f cli = 14 mhz v vi = 2.0 v, no load f inh = 15.4 khz pw inh = 5.0 m s 10.0 ma remarks 1. v of : output applied voltage, v o : output voltage without load 2. the reference values are typical values only. the output deviation is only guaranteed within the chip.
19 m m m m pd16448a switching characteristics (t a = -30 to +85 c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit t phl c l = 20 pf 10 54 ns start pulse propagation delay time t plh c l = 20 pf 10 54 ns maximum clock frequency 1 f max. 1 15 mhz maximum clock frequency 2 f max. 2 with 3-phase clock input 8 mhz logic input capacitance c i1 other than sthl, sthr 15 pf sthl, sthr input capacitance c i2 sthl, sthr 20 pf video input capacitance c 3 c 1 to c 3 , v vi = 2.0 v 50 pf timing requirements (t a = -30 to +85 c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit clock pulse width pw cli duty = 50 % 33 ns start pulse setup time t setup 8ns start pulse hold time t hold 8ns reset pulse width pw res 66 ns inh setup time t isetup 33 ns inh hold time t ihold 33 ns reset-inh time t r-i 81 ns inh pulse width pw inh 5clk remark keep the rise and fall times of the logic input signals to within t r = t f = 5 ns (10 to 90%). as an example, the switching characteristic wave of cli 1 is defined on the next page.
20 m m m m pd16448a switching characteristic wave (simultaneous/successive sampling) start pulse input timing start pulse output timing cli 1 v dd1 v ss1 sthl (sthr) v oh v ol 50 % 50 % t plh 50 % 50 % t phl remark the input/output timing of the start pulse is the same for simultaneous/successive sampling. cli 1 v dd1 v ss1 sthr (sthl) v dd1 v ss1 shp 1 (shp 240 ) v dd1 v ss1 50 % 50 % pw cli1 pw cli1 50 % 50 % t setup t hold
21 m m m m pd16448a reset inh pulse timing cli 1 reset inh pw res t isetup t iihold pw inh t r-i 50% 50% 50% 50% 50% h
22 m m m m pd16448a 4. recommended conditions for installation this product should be installed under the following recommended conditions. consult one of our sales representatives for installation under conditions other than those recommended. installation condition installation method condition soldering heat with heating tool at 300 c to 350 c under pressure of 100 g (per pin) for 2 to 3 seconds thermocompression bonding acf (sheet type adhesive agent) temporary adhesion at 70 c to 100 c under pressure of 3 to 8 kg/cm 2 for 3 to 5 seconds permanent adhesion at 165 c to 180 c under pressure of 25 to 45 kg/cm 2 for 30 to 40 seconds (when aeolotropic conductive film sumizac 1003 from sumitomo bakelite co., ltd. is used) caution for installation conditions for the acf part, contact the acf manufacturer beforehand. do not mix different installation methods.
23 m m m m pd16448a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m m m m pd16448a reference nec semiconductor device reliability/quality control system quality grade on nec semiconductor devices c10983e c11531e no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

▲Up To Search▲

Price & Availability of UPD16448A

	To Download UPD16448A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .